ARM System Developer's Guide: Designing and Optimizing by Andrew Sloss, Dominic Symes, Chris Wright

By Andrew Sloss, Dominic Symes, Chris Wright

The booklet is especially good written and the language is straightforward to appreciate, so long as you've got a few uncomplicated wisdom approximately meeting language and C programming.

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Additional resources for ARM System Developer's Guide: Designing and Optimizing System Software (The Morgan Kaufmann Series in Computer Architecture and Design)

Example text

A coprocessor extends the processing features of a core by extending the instruction set or by providing configuration registers. More than one coprocessor can be added to the ARM core via the coprocessor interface. The coprocessor can be accessed through a group of dedicated ARM instructions that provide a load-store type interface. Consider, for example, coprocessor 15: The ARM processor uses coprocessor 15 registers to control the cache, TCMs, and memory management. The coprocessor can also extend the instruction set by providing a specialized group of new instructions.

The Jazelle instruction set is a closed instruction set and is not openly available. 3 gives the Jazelle instruction set features. 4 Interrupt Masks Interrupt masks are used to stop specific interrupt requests from interrupting the processor. There are two interrupt request levels available on the ARM processor core—interrupt request (IRQ) and fast interrupt request (FIQ). The cpsr has two interrupt mask bits, 7 and 6 (or I and F ), which control the masking of IRQ and FIQ, respectively. The I bit masks IRQ when set to binary 1, and similarly the F bit masks FIQ when set to binary 1.

If the decode stage sees a coprocessor instruction, then it offers it to the relevant coprocessor. But if the coprocessor is not present or doesn’t recognize the instruction, then the ARM takes an undefined instruction exception, which allows you to emulate the behavior of the coprocessor in software. 6 Architecture Revisions Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation. The ISA has evolved to keep up with the demands of the embedded market.

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