Combinatorial Algorithms for Integrated Circuit Layout by Thomas Lengauer

By Thomas Lengauer

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2. 3. (a) Structure of the adder generated with the statement adder( 4, true, d); (b) folded hierarchy of this adder. by from six to well over a dozen masks. We will not describe in detail how the masks guide the fabrication process. For more information on this topic, the reader is referred to introductory textbooks on design of very large-scale integrated (VLSI) circuits, such as [313, 334, 460]. To produce a technically functioning circuit, we must ensure that the images on each mask meet certain requirements, and that the different masks are consistent with respect to one another.

As a rule, full-custom design technologies allow for arbitrary twodimensional placement of rectangular block layouts on initially empty silicon, perhaps involving floorplanning. 1 shows a layout that is composed of several blocks that are arranged on the chip surface and connected by wires through intervening routing channels. The part of the layout process that places and routes the rectangular blocks is also called general-cell placement. Furthermore, a full-custom layout procedure provides a large variety of geometries for block layouts.

1 Basic Definitions In this chapter, we will lay the mic problems arising in circuit the beginning, so as to be able with which we will be working. algorithmic problem. 1 formal framework for discussing the algorithlayout. 1 (Algorithmic Problem) An algorithmic problem II is a mapping II : I --+ 25 , where I is the set of problem instances and S is the set of configurations. For a problem instance pEl, the configurations in II(p) are called solutions of p or legal configurations for p. Both I and S may be infinite sets.

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