Compilation Techniques for Reconfigurable Architectures by João M.P. Cardoso, Pedro C. Diniz

By João M.P. Cardoso, Pedro C. Diniz

This ebook describes quite a lot of code adjustments and mapping suggestions for compiling courses written in high-level programming languages to reconfigurable architectures. whereas lots of those ameliorations and mapping concepts were built within the context of compilation for normal architectures and high-level synthesis, their software to reconfigurable architectures poses an entire new set of demanding situations- quite whilst focusing on fine-grained reconfigurable architectures comparable to modern Field-Programmable Gate-Arrays (FPGAs).

Organized in 8 chapters, this booklet offers a invaluable constitution for practitioners and graduate scholars within the region of laptop technological know-how and electric and desktop engineering to successfully map computations to reconfigurable architectures.

Key Features:

  • Introduces the reader to compilation and reconfigurable computing architectures.
  • Presents a number compiler code variations and mapping strategies concentrating on critical programming languages.
  • Allows the reader to bridge the space among the software program compilation and the compilation and synthesis domains.
  • Brings a few compilation ideas jointly into one established resource, and contains consultant examples in their applications.

  • Provides a historic viewpoint on consultant compilation learn efforts over the past 15 years.

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Extra resources for Compilation Techniques for Reconfigurable Architectures

Sample text

In this example, configuration 1 is being executed while portion b of configuration 2 is being loaded and programmed onto the reconfigurable fabric. Partial reconfiguration can be fine- or coarse-grained. , to specify a new constant value). In a coarse-grained partial reconfiguration, it is possible to change sets of FUs and interconnection resources based on columns, rows, or selected regions. With RPUs that allow partial reconfiguration, it is possible to reconfigure regions of the RPU while others are executing.

It checks the configuration controller ports and based on the value of the event starts the next configuration step. In this kind of architecture, prefetching is used to amortize the time required for loading the configuration data onto the internal configuration cache. However, whenever a configuration is not in cache, the configuration controller has to fetch it from the external memory. In the case of the XPP, the configuration controller initiates the programming of a subsequent configuration as soon as it is determined and the execution of the current configuration has terminated.

Although conceptually simple, high-level synthesis hides many challenging aspects. For instance, the scheduling is highly dependent on the mapping of data to memories and the number of data ports they offer as well as the use of pipelined components as are the cases with multipliers and RAMs. , FU types and instances) as well as the mapping of array variables to RAM modules. In addition, the input language allows for users to specify which loops should be unrolled and in some case by how much. These facilities allow designers to explore a wide range of hardware implementations for a variety of resources and memory mapping settings.

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