Designing TSVs for 3D Integrated Circuits by Nauman Khan

By Nauman Khan

This e-book explores the demanding situations and provides top innovations for designing Through-Silicon Vias (TSVs) for 3D built-in circuits. It describes a unique strategy to mitigate TSV-induced noise, the GND Plug, that is better to others tailored from 2-D planar applied sciences, corresponding to a bottom floor airplane and standard substrate contacts. The ebook additionally investigates, within the type of a comparative learn, the impression of TSV measurement and granularity, spacing of C4 connectors, off-chip energy supply community, shared and devoted TSVs, and coaxial TSVs at the caliber of strength supply in 3-D ICs. The authors supply particular top layout practices for designing three-D strength supply networks. because TSVs occupy silicon real-estate and impression machine density, this booklet presents 4 iterative algorithms to reduce the variety of TSVs in an influence supply community. not like different latest equipment, those algorithms could be utilized in early layout levels whilst in basic terms useful block- point behaviors and a floorplan can be found. eventually, the authors discover using Carbon Nanotubes for strength grid layout as a futuristic replacement to Copper.

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Extra resources for Designing TSVs for 3D Integrated Circuits

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The first column shows the technique used to integrate coaxial TSV into the 3-D PDN. The next three columns quantify three parameters (number of blockages, size of each blockage, and the number of additional signal routes) that we use to compare the implementations. The last column summarizes the main benefit obtained from each integration technique. Clearly, coaxial TSVs present an exciting opportunity to reduce the number of blockages, integrate extra decoupling capacitance, and provide additional signal routes.

We can make the following observations: • The ACCL, directly connected to C4 bumps, exhibits nearly constant maximum and average IR drops across the different TSV sizes. As TSV size is increased, there is a slight increase in both maximum and average IR drop. This represents the fact that the grid sharing capability is improved with the increased TSV size. • More importantly, the IR drop saturates in PROC and MEM for TSV sizes of and greater than 20 μm. Such saturation suggests the lack of benefit of increasing the TSV size beyond a specific size.

An initial circuit is generated assuming uniform ni for each grid node. 3 Power TSV Minimization Algorithms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 47 Input: An initial design with an abundance of TSVs Output: The minimum ni for each grid node such that each node meets the voltage budget mark all device nodes gki, j “not done” initialize noOfNodesDone to zero run SPICE while noOfNodesDone < M do let gs denote the device node that is “not done” and has largest voltage pick node tx which is gs ’s direct TSV neighbor that has the largest slack decrement nx by 1 run SPICE if circuit fails then increment nx by 1 pick the second neighboring TSV node ty decrement ny by 1 run SPICE if circuit fails then increment ny by 1 mark gs “done” increment noOfNodesDone by 1; end end end Algorithm 1: REDUCE MAXIMUM SLACK (RMS) block.

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