By Ashok B. Mehta
This e-book presents a hands-on, application-oriented advisor to the language and technique of either SystemVerilog Assertions and SytemVerilog practical assurance. Readers will enjoy the step by step method of sensible verification, to be able to allow them to discover hidden and difficult to discover insects, element on to the resource of the malicious program, offer for a fresh and straightforward strategy to version advanced timing tests and objectively resolution the query ‘have we functionally tested everything’. Written by way of a certified end-user of either SystemVerilog Assertions and SystemVerilog sensible assurance, this e-book explains each one inspiration with effortless to appreciate examples, simulation logs and purposes derived from actual tasks. Readers may be empowered to take on the modeling of complicated checkers for useful verification, thereby significantly lowering their time to layout and debug.
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Additional info for SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
This assertion works like any other. For example, if the ‘Read Cache Latency’ is greater than 2 clocks, fire the assertion. This is an easy to write assertion with very useful return. 9 Protocol for Adding Assertions • Do not duplicate RTL – White box observability does not mean adding an assertion for each line of RTL code. This is a very important point, in that if RTL says ‘req’ means ‘grant’, don’t write an assertion that says the same thing!! Read on. – Capture the intent For example, a Write that follows a Read to the same address in the request pipe will always be allowed to finish before the Read.
7 Clocking basics As mentioned before, a concurrent assertion is evaluated only on the occurrence of an ‘edge’, known as the ‘sampling edge’. The reason for continually mentioning this ‘edge’ as ‘clk’ is because it is best to have this ‘edge’ synchronous to either posedge or negedge for a signal. You can indeed have an asynchronous edge as well. BUT be very careful.
After you have exhausted constrained random verification, you now want to simulate a final massive random verification, blasting transactions from all input interfaces and firing transactions from internal masters (DMA, Video Engine, Embedded processors) to all the output interfaces of the design. – BUT there’s a good chance your reference models, self-checking tests, scoreboards may not be able to predict the correct behavior of the design under such massive randomness. ) unless they are full proof to massive random transaction streams.